Volume 22, Issue 4 (JIAEEE Vol.22 No.4 2025)                   Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(4): 28-40 | Back to browse issues page

XML Persian Abstract Print

Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
Souri A, Mavaddati S, Gholami M. Automatic Wafer Defect Detection in Integrated Circuits Using Deep Learning Models. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (4) :28-40
URL: http://jiaeee.com/article-1-1769-en.html
Automatic Wafer Defect Detection in Integrated Circuits Using Deep Learning Models
Ali Souri , Samira Mavaddati * , Mohammad Gholami
Electronic Department, Faculty of Engineering and Technology, University of Mazandaran, Babolsar
Abstract:   (700 Views)
This study proposes a deep learning-based framework for automatic wafer defect detection in integrated circuits. Several architectures, including Recurrent Neural Networks (RNN), VGG16, MobileNet, GoogleNet, ResNet-based models, and DenseNet121, were implemented and comparatively evaluated. The employed dataset consisted of wafer images with various defect types, which were preprocessed and augmented using techniques such as rotation, brightness adjustment, and noise injection. Model performance was assessed based on Accuracy, Sensitivity, Recall, and F-measure. The results clearly indicate that deep learning models significantly outperform traditional image processing methods, with DenseNet121 achieving the highest accuracy of 98.33%. Furthermore, the comparative analysis revealed that deeper architectures with advanced feature extraction capabilities substantially improve defect detection performance. This research not only highlights the effectiveness of deep models for semiconductor manufacturing but also provides a comprehensive reference for researchers and industry practitioners aiming to enhance defect detection systems and ensure higher quality in integrated circuits.
 
Keywords: Wafer defect detection, Semiconductor industry, Integrated circuits, Image processing, Convolutional neural networks, Deep learning.
Full-Text [PDF 1339 kb]   (144 Downloads)    
Type of Article: Research | Subject: Electronic
Received: 2024/10/27 | Accepted: 2025/09/11 | Published: 2026/01/22
References
1. [1] J. Yu et al., "Wafer map defect recognition based on deep transfer learning-based densely connected convolutional network and deep forest", Engineering Applications of Artificial Intelligence, vol. 105, 2021. [DOI:10.1016/j.engappai.2021.104387]
2. [2] R. Li and Z. Kang, "Deep Learning for Wafer Map Defect Detection: A Review", in 2023 Global Reliability and Prognostics and Health Management Conference (PHM-Hangzhou), 2023, doi: 10.1109/PHM-Hangzhou58797.2023.10482800. [DOI:10.1109/PHM-Hangzhou58797.2023.10482800]
3. [3] U. Batool, M. I. Shapiai, M. Tahir, A. Elfakharany et al., "A Systematic Review of Deep Learning for Silicon Wafer Defect Recognition", IEEE Access, vol. 99, pp. 1-1, Aug. 2021, doi: 10.1109/ACCESS.2021.3106171. [DOI:10.1109/ACCESS.2021.3106171]
4. [4] C.-Y. Hsu and J.-C. Chien, "Ensemble convolutional neural networks with weighted majority for wafer bin map pattern classification", Journal of Intelligent Manufacturing, vol. 33, no. 4, Feb. 2022, doi: 10.1007/s10845-020-01687-7. [DOI:10.1007/s10845-020-01687-7]
5. [5] S. Cheon, H. Lee, C. O. Kim, and S. H. Lee, "Convolutional neural network for wafer surface defect classification and the detection of unknown defect class", IEEE Transactions on Semiconductor Manufacturing, vol. 32, no. 2, pp. 163-170, 2019, doi: 10.1109/TSM.2019.2902657. [DOI:10.1109/TSM.2019.2902657]
6. [6] J. Chien, M. Wu, and J. Lee, "Inspection and classification of semiconductor wafer surface defects using CNN deep learning networks", Applied Sciences, 2020. [DOI:10.3390/app10155340]
7. [7] I. Jeong, S. Y. Lee, K. Park et al., "Wafer map failure pattern classification using geometric transformation-invariant convolutional neural network", Scientific Reports, vol. 13, p. 8127, 2023, doi: 10.1038/s41598-023-34147-2. [DOI:10.1038/s41598-023-34147-2]
8. [8] K. K. Chauhan, G. Joshi, M. M. Kaur, and R. Vig, "Semiconductor wafer defect classification using convolution neural network: A binary case", IOP Conference Series: Materials Science and Engineering, vol. 1225, 2022. [DOI:10.1088/1757-899X/1225/1/012060]
9. [9] P. P. Shinde, P. P. Pai, and S. P. Adiga, "Wafer defect localization and classification using deep learning techniques", IEEE Access, vol. 10, pp. 39969-39974, 2022, doi: 10.1109/ACCESS.2022.3166512. [DOI:10.1109/ACCESS.2022.3166512]
10. [10] F. López de la Rosa, J. Gómez-Sirvent, R. Morales, R. Sánchez-Reolid, and A. Fernández-Caballero, "Defect detection and classification on semiconductor wafers using two-stage geometric transformation-based data augmentation and SqueezeNet lightweight convolutional neural network", Computers & Industrial Engineering, vol. 183, p. 109549, 2023, doi: 10.1016/j.cie.2023.109549. [DOI:10.1016/j.cie.2023.109549]
11. [11] S. Kim and D. Kim, "A novel approach for wafer defect pattern classification based on topological data analysis", Expert Systems with Applications, vol. 231, 2023, doi: 10.1016/j.eswa.2023.120765. [DOI:10.1016/j.eswa.2023.120765]
12. [12] Z. Li, Z. Wang, and W. Shi, "Automatic wafer defect classification based on decision tree of deep neural network", in 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2022, pp. 1-6, doi: 10.1109/ASMC54647.2022.9792500. [DOI:10.1109/ASMC54647.2022.9792500]
13. [13] M. B. Alawieh, D. Boning, and D. Z. Pan, "Wafer map defect patterns classification using deep selective learning", in 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2020, pp. 1-6, doi: 10.1109/DAC18072.2020.9218580. [DOI:10.1109/DAC18072.2020.9218580]
14. [14] Y. Chen, M. Zhao, Z. Xu, K. Li, and J. Ji, "Wafer defect recognition method based on multi-scale feature fusion", Frontiers in Neuroscience, 2023, doi: 10.3389/fnins.2023.1202985. [DOI:10.3389/fnins.2023.1202985]
15. [15] J. Li, T. Ran, C. Renxiang, C. Yongpeng, Z. Chengying, and H. Xianzhen, "Sample-imbalanced wafer map defects classification based on auxiliary classifier denoising diffusion probability model", Computers & Industrial Engineering, vol. 192, p. 110209, 2024. [DOI:10.1016/j.cie.2024.110209]
16. [16] Y. Wang, Y. Wei, and H. Wang, "A class imbalanced wafer defect classification framework based on variational autoencoder generative adversarial network", Measurement Science and Technology, vol. 34, no. 2, 2023, doi: 10.1088/1361-6501 [DOI:10.1088/1361-6501/ac9ed3]
17. [17] E. Shin and C. D. Yoo, "Efficient convolutional neural networks for semiconductor wafer bin map classification", Sensors (Basel), vol. 23, no. 4, 2023, doi: 10.3390/s23041926. [DOI:10.3390/s23041926]
18. [18] J. A. Mat-Jizat, A. P. Abdul Majeed, A. F. Ab. Nasir, and Z. Taha, "Evaluation of the machine learning classifier in wafer defects classification", ICT Express, vol. 7, pp. 535-539, 2021. [DOI:10.1016/j.icte.2021.04.007]
19. [19] J. Ma, T. Zhang, C. Yang, Y. Cao, L. Xie, H. Tian, and X. Li, "Review of Wafer Surface Defect Detection Methods", Electronics, vol. 12, p. 1787, 2023, doi: 10.3390/electronics12081787. [DOI:10.3390/electronics12081787]
20. [20] A. Shawon, M. O. Faruk, M. B. Habib, and A. M. Khan, "Silicon Wafer Map Defect Classification Using Deep Convolutional Neural Network With Data Augmentation", in 2019 IEEE 5th International Conference on Computer and Communications (ICCC), Chengdu, China, 2019, pp. 1995-1999, doi: 10.1109/ICCC47050.2019.9064029. [DOI:10.1109/ICCC47050.2019.9064029]
21. [21] Kaggle, "WM811K Wafer Map Dataset", available: https://www.kaggle.com/datasets/qingyi/wm811k-wafer-map.
22. [22] Kaggle, "Wafermap Dataset", available: https://www.kaggle.com/datasets/shawon10/wafermap.
23. [23] S.-K. Fan and S.-H. Chiu, "A new ViT-Based augmentation framework for wafer map defect classification to enhance the resilience of semiconductor supply chains", International Journal of Production Economics, vol. 273, p. 109275, 2024. [DOI:10.1016/j.ijpe.2024.109275]
24. [24] Y. Sheng, J. Yan, and M. Piao, "Improved wafer map defect pattern classification using automatic data augmentation based lightweight encoder network in contrastive learning", Journal of Intelligent Manufacturing, 2024, doi: 10.1007/s10845-024-02444-w. [DOI:10.1007/s10845-024-02444-w]
25. [25] P. Bhatnagar, T. Arora, and R. Chaujar, "Semiconductor Wafer Map Defect Classification Using Transfer Learning", in 2022 IEEE Delhi Section Conference (DELCON), New Delhi, India, 2022, pp. 1-4, doi: 10.1109/DELCON54057.2022.9753436. [DOI:10.1109/DELCON54057.2022.9753436]
26. [26] S. Chen, Y. Zhang, M. Yi, J. Ma, and X. Hou, "Wafer maps defect recognition based on transfer learning of handwritten pre-training network", in 2021 International Symposium on Computer Technology and Information Science (ISCTIS), Guilin, China, 2021, pp. 280-283, doi: 10.1109/ISCTIS51085.2021.00064. [DOI:10.1109/ISCTIS51085.2021.00064]
27. [27] S. Mavaddati and H. S. Azhari Lamraski, "Brain tumor detection and classification based on MRI images using deep learning and transfer learning models", Journal of Iranian Association of Electrical and Electronics Engineers, vol. 22, no. 2, pp. 129-141, 2025. [DOI:10.61882/jiaeee.22.2.129]
28. [28] A. Hatami and I. GanjKhani, "Long-term voltage stability assessment of an integrated transmission distribution system based on LSTM recurrent neural network", Journal of Iranian Association of Electrical and Electronics Engineers, vol. 21, no. 4, pp. 123-133, 2024. [DOI:10.61186/jiaeee.21.4.123]
Add your comments about this article : Your username or Email:
CAPTCHA
Send email to the article author

Rights and permissions
Creative Commons License This Journal is an open access Journal Licensed under the Creative Commons Attribution-NonCommercial 4.0 International License. (CC BY NC 4.0)