Volume 22, Issue 4 (JIAEEE Vol.22 No.4 2025)                   Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(4): 0-0 | Back to browse issues page

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Mavaddati S, Souri A, Gholami M. Automatic Wafer Defect Detection in Integrated Circuits Using Deep Learning Models. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (4)
URL: http://jiaeee.com/article-1-1769-en.html
Automatic Wafer Defect Detection in Integrated Circuits Using Deep Learning Models
Samira Mavaddati * , Ali Souri , Mohammad Gholami
University of Mazandaran
Abstract:   (67 Views)
This study proposes a deep learning-based framework for automatic wafer defect detection in integrated circuits. Several architectures, including Recurrent Neural Networks (RNN), VGG16, MobileNet, GoogleNet, ResNet-based models, and DenseNet121, were implemented and comparatively evaluated. The employed dataset consisted of wafer images with various defect types, which were preprocessed and augmented using techniques such as rotation, brightness adjustment, and noise injection. Model performance was assessed based on Accuracy, Sensitivity, Recall, and F-measure. The results clearly indicate that deep learning models significantly outperform traditional image processing methods, with DenseNet121 achieving the highest accuracy of 98.33%. Furthermore, the comparative analysis revealed that deeper architectures with advanced feature extraction capabilities substantially improve defect detection performance. This research not only highlights the effectiveness of deep models for semiconductor manufacturing but also provides a comprehensive reference for researchers and industry practitioners aiming to enhance defect detection systems and ensure higher quality in integrated circuits.
 
Keywords: Wafer defect detection, Semiconductor industry, Integrated circuits, Image processing, Convolutional neural networks, Deep learning.
     
Type of Article: Research | Subject: Electronic
Received: 2024/10/27 | Accepted: 2025/09/11
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