Volume 22, Issue 4 (JIAEEE Vol.22 No.4 2025)
Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(4): 131-138 |
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shekarriz Fomani M, Niaraki Asli R. Design of a Fully Hardened Latch Against SEDU with Input Transient Fault Filtering Capability Using an Enhanced C-Element. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (4) :131-138
URL: http://jiaeee.com/article-1-1698-en.html
URL: http://jiaeee.com/article-1-1698-en.html
University of Guilan
Abstract: (6 Views)
As transistor dimensions, supply voltage levels, and node capacitances continue to scale down in modern nanoscale technologies, digital circuits become increasingly susceptible to soft errors, including input transient faults, single-node single-event upsets, and single-node double-event upsets. Therefore, designing robust latches is essential to maintain reliability and ensure stable circuit operation. In this work, a fully hardened latch immune to single-event double-node upsets and capable of filtering input transient faults is proposed, in which an enhanced C-element is employed as the primary mechanism for preventing fault propagation. Simulations performed using Gate-All-Around (GAA) technology indicate that, compared to competing designs, the proposed latch reduces power consumption by 34.77% to 73.80%, decreases propagation delay by 1.84% to 23.38%, and improves the power–delay product by 8.87% to 71.24%. Moreover, the proposed latch effectively filters input transient faults with pulse widths up to 7.9 ps. In addition, Monte Carlo analysis demonstrates that the proposed design exhibits significant robustness against process variations and environmental fluctuations.
Keywords: Fully hardened Latch, single-event double-node upsets, Input Transient Fault, Gate-All-Around Technology, Power-Delay Product
Type of Article: Research |
Subject:
Electronic
Received: 2024/02/21 | Accepted: 2025/12/19 | Published: 2026/02/6
Received: 2024/02/21 | Accepted: 2025/12/19 | Published: 2026/02/6
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