Volume 18, Issue 4 (JIAEEE Vol.18 No.4 2021)
Journal of Iranian Association of Electrical and Electronics Engineers 2021, 18(4): 1-7 |
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Babazadeh Daryan B, Khalesi H, Ghods V, Izadbakhsh A. Design of Four-Stage OTA CMOS with Low Area. Journal of Iranian Association of Electrical and Electronics Engineers 2021; 18 (4) :1-7
URL: http://jiaeee.com/article-1-1171-en.html
URL: http://jiaeee.com/article-1-1171-en.html
Garmsar Branch, Islamic Azad University, Garmsar, Iran
Abstract: (2979 Views)
Operational amplifiers are one of the most widely used basic blocks in analog and mixed systems. In this paper, a four-stage transduction operational amplifier with low die occupancy is proposed. In this structure, an all-differential block is used as the fourth stage and the compensation network. The proposed amplifier compensation is done with a single and small MOSCAP. This has improved the GBW and FOM because of reducing the number and amount of the compensating capacitor while reducing the die occupancy. The simplicity and robustness of the proposed design make it possible to implement in a chip with dimensions of 210x250 μm. The proposed four-stage amplifier is simulated using standard TSMC 0.18µ CMOS technology. The advantage of the design is the presentation of a structure that can be implemented and is robust to changes in circuit parameters in implementation. According to simulation, DC gain, power consumption, slew rate, GBW, and PM are obtained 120dB, 545µW, 2.12 V/µS, 16.4 MHz, and 88⁰, respectively.
Type of Article: Research |
Subject:
Electronic
Received: 2020/08/21 | Accepted: 2021/05/1 | Published: 2021/10/14
Received: 2020/08/21 | Accepted: 2021/05/1 | Published: 2021/10/14
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