Volume 22, Issue 1 (JIAEEE Vol.22 No.1 2025)                   Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(1): 65-77 | Back to browse issues page


XML Persian Abstract Print


Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:

Bazli M, Es'haghi S, Shahi M, Naseh M. Simultaneous analysis of the stochastic transistor aging and process variation in digital systems by developing machine learning-based models for standard cells. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (1) :65-77
URL: http://jiaeee.com/article-1-1601-en.html
Bijand Branch - Islamic Azad University
Abstract:   (716 Views)
Nowadays, reliability is one of the most important challenges in the design of nanometer circuits. Transistor aging and process variation are two important factors affecting reliability. After the circuits start to work, transistors age gradually, which means that the characteristics of transistors and in particular their threshold voltage degrade. As a result, delay increases and eventually causes violation of timing constraints and incorrect operation of the circuit. Various phenomena cause the transistor aging, among them BTI is the most important. This phenomenon reveals has stochastic nature in today's advanced manufacturing technologies, and atomic models exist to describe it. Process variation due to the non-ideality of the manufacturing process and often under the influence of the lithography process appears as a stochastic difference in the characteristics of the transistors produced with the expected values after manufacturing. The simultaneous analysis of these phenomena is vital to improve the design. Today, the starting point of digital systems design has raised to higher abstraction levels. As a consequent, we need fast and accurate models to evaluate the reliability of circuits in order effective exploration of the design space. In this article, first, machine learning based models are developped for standard cells. Then, a Monte Carlo-based analysis method is proposed for the simultaneous analysis of aging and process variation. The experimental results show an improvement in analysis time with an average of 94% compared to existing methods. This improvement has been achieved while maintaining the accuracy of the analysis. Of course, to achieve this improvement, a lot of time is spent on training the models, which is done once and offline and has no effect on the execution time.
Full-Text [PDF 1081 kb]   (118 Downloads)    
Type of Article: Research | Subject: Electronic
Received: 2023/05/22 | Accepted: 2024/09/10 | Published: 2025/05/29

References
1. [1] International Roadmap for Devices and Systems (IRDS™) 2022 Edition, 2022 https://irds.ieee.org/editions/2022.
2. [2] S. K. Kishore, T. R. Patnala, A. S. Tigadi, and A. Jamshed, "An On-chip Analysis of the VLSI designs under Process Variations", in 2020 International Conference on Smart Electronics and Communication (ICOSEC), 2020, pp. 1273-1277: IEEE [DOI:10.1109/ICOSEC49089.2020.9215244]
3. [3] E. Maricau, G. Gielen, E. Maricau, and G. Gielen, "Analog IC Reliability Simulation", Analog IC Reliability in Nanometer CMOS, pp. 93-149, 2013. [DOI:10.1007/978-1-4614-6163-0_5]
4. [4] T. Grasser, Bias temperature instability for devices and circuits. Springer Science & Business Media, 2013. [DOI:10.1007/978-1-4614-7909-3]
5. [5] J. F. Zhang, R. Gao, M. Duan, Z. Ji, W. Zhang, and J. Marsland, "Bias temperature instability of mosfets: Physical processes, models, and prediction", Electronics, vol. 11, no. 9, p. 1420, 2022. [DOI:10.3390/electronics11091420]
6. [6] B. Kaczer et al., "Atomistic approach to variability of bias-temperature instability in circuit simulations", in 2011 International Reliability Physics Symposium, 2011, pp. XT. 3.1-XT. 3.5: IEEE. [DOI:10.1109/IRPS.2011.5784604]
7. [7] S. Kiamehr et al., "The impact of process variation and stochastic aging in nanoscale VLSI", in 2016 IEEE International Reliability Physics Symposium (IRPS), 2016, pp. CR-1-1-CR-1-6: IEEE. [DOI:10.1109/IRPS.2016.7574590]
8. [8] S. Es' haghi and M. Eshghi, "Aging-aware scheduling and binding in high-level synthesis considering workload effects", Microelectronics Reliability, vol. 106, p. 113549, 2020. [DOI:10.1016/j.microrel.2019.113549]
9. [9] A. Sheikholeslami, "Process variation and pelgrom's law [Circuit intuitions]", IEEE Solid-State Circuits Magazine, vol. 7, no. 1, pp. 8-9, 2015. [DOI:10.1109/MSSC.2014.2369331]
10. [10] Y. Lu, L. Shang, H. Zhou, H. Zhu, F. Yang, and X. Zeng, "Statistical reliability analysis under process variation and aging effects", in Proceedings of the 46th Annual Design Automation Conference, 2009, pp. 514-519. [DOI:10.1145/1629911.1630044]
11. [11] S. Es' haghi and M. Eshghi, "Lifetime-aware scheduling in high level synthesis", Microelectronics Reliability, vol. 91, pp. 86-97, 2018. [DOI:10.1016/j.microrel.2018.06.016]
12. [12] S. Mahapatra and N. Parihar, "A review of NBTI mechanisms and models", Microelectronics Reliability, vol. 81, pp. 127-135, 2018. [DOI:10.1016/j.microrel.2017.12.027]
13. [13] Y. Xue et al., "On the understanding of pMOS NBTI degradation in advance nodes: Characterization, modeling, and exploration on the physical origin of defects", IEEE Transactions on Electron Devices, 2023. [DOI:10.1109/TED.2023.3294460]
14. [14] S. Mahapatra and N. Parihar, "Modeling of NBTI using BAT framework: DC-AC stress-recovery kinetics, material, and process dependence", IEEE Transactions on Device and Materials Reliability, vol. 20, no. 1, pp. 4-23, 2020. [DOI:10.1109/TDMR.2020.2967696]
15. [15] N. Ghobadi and A. Afzali-Kusha, "Investigation and Modeling of Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) Induced Degradation in Multi-Gate Nano-Devices", (in eng), Journal of Iranian Association of Electrical and Electronics Engineers, Research vol. 12, no. 2, pp. 1-14, 2015.
16. [16] W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao, "The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 2, pp. 173-183, 2009. [DOI:10.1109/TVLSI.2008.2008810]
17. [17] M. Mohammadi, "A High-Speed Dual-Bit Parallel Adder based on Carbon Nanotube ‎FET technology for use in arithmetic units", (in eng), Journal of Iranian Association of Electrical and Electronics Engineers, Research vol. 20, no. 1, pp. 107-118, 2023. [DOI:10.52547/jiaeee.20.1.107]
18. [18] Synopsys | EDA Tools, Semiconductor IP and Application Security solutions. https://www.synopsys.com/content/ dam/synopsys/verification/white-papers/mosra-wp.pdf
19. [19] D. Mahajan and V. Ruparelia, "Reliability Simulation and Analysis of Important RF Circuits Using Cadence Relxpert", in 2018 IEEE Int. Conf. Electronics, Comput. Communication Technol. (CONECCT), Bangalore, Mar. 16-17, 2018. IEEE, 2018. [DOI:10.1109/CONECCT.2018.8482396]
20. [20] M. Gholami, P. Valipour, and H. Alamdar, "One-bit Full Adder with Low Delay and Low Cell Count in the Emerging Technology of Quantum-Dot Cellular Automata", (in eng), Journal of Iranian Association of Electrical and Electronics Engineers, Research vol. 21, no. 1, pp. 11-16, 2024. [DOI:10.61186/jiaeee.21.1.11]
21. [21] R. Wang, Z. Zhang, Z. Sun, Z. Guo, Y. Lin, and R. Huang, "Cross-Layer Design for Reliability in Advanced Technology Nodes: An EDA Perspective", in 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2022, pp. 1-4: IEEE. [DOI:10.1109/ICSICT55466.2022.9963318]
22. [22] D. Lorenz, "Aging analysis of digital integrated circuits", Universitätsbibliothek der TU München, 2012.
23. [23] L. C. Acharya et al., "Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024. [DOI:10.1109/TCAD.2024.3396432]
24. [24] L. Wu et al., "Glacier: A hot carrier gate level circuit characterization and simulation system for VLSI design", in Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525), 2000, pp. 73-79: IEEE.
25. [25] J. Chen, S. Wang, N. Bidokhti, and M. Tehranipoor, "A framework for fast and accurate critical-reliability paths identification", in IEEE North Atlantic test workshop (NATW), 2011, pp. 1-4.
26. [26] D. Lorenz, M. Barke, and U. Schlichtmann, "Efficiently analyzing the impact of aging effects on large integrated circuits", Microelectronics Reliability, vol. 52, no. 8, pp. 1546-1552, 2012. [DOI:10.1016/j.microrel.2011.12.029]
27. [27] X. Xhafa, A. D. Güngördü, D. Erol, Y. Yavuz, and M. B. Yelten, "An automated setup for the characterization of time-based degradation effects including the process variability in 40-nm CMOS transistors", IEEE Transactions on Instrumentation and Measurement, vol. 70, pp. 1-10, 2021. [DOI:10.1109/TIM.2021.3090175]
28. [28] M. Raji and B. Ghavami, "Lifetime Reliability Optimization Algorithms of Integrated Circuits Using Dual-Threshold Voltage Assignment", in Lifetime Reliability-aware Design of Integrated Circuits: Springer, 2022, pp. 85-105. [DOI:10.1007/978-3-031-15345-7_6]
29. [29] V. V. Camargo, B. Kaczer, G. Wirth, T. Grasser, and G. Groeseneken, "Use of SSTA tools for evaluating BTI impact on combinational circuits", IEEE transactions on very large scale integration (VLSI) systems, vol. 22, no. 2, pp. 280-285, 2013. [DOI:10.1109/TVLSI.2013.2240323]
30. [30] P. R. Genssler, H. E. Barkam, K. Pandaram, M. Imani, and H. Amrouch, "Modeling and predicting transistor aging under workload dependency using machine learning", IEEE Transactions on Circuits and Systems I: Regular Papers, 2023. [DOI:10.1109/TCSI.2023.3289325]
31. [31] A. Bu and J. Li, "A learning-based framework for circuit path level NBTI degradation prediction", Electronics, vol. 9, no. 11, p. 1976, 2020. [DOI:10.3390/electronics9111976]
32. [32] L. Alrahis, J. Knechtel, F. Klemme, H. Amrouch, and O. Sinanoglu, "GNN4REL: Graph neural networks for predicting circuit reliability degradation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 3826-3837, 2022. [DOI:10.1109/TCAD.2022.3197521]
33. [33] T. Mohamed, V. M. van Santen, L. Alrahis, O. Sinanoglu, and H. Amrouch, "Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability", IEEE Transactions on Circuits and Systems I: Regular Papers, 2024. [DOI:10.1109/TCSI.2024.3397460]
34. [34] P. J. Kumar and M. Mini, "Machine learning based workload balancing scheme for minimizing stress migration induced aging in multicore processors", International Journal of Information Technology, vol. 15, no. 1, pp. 399-410, 2023. [DOI:10.1007/s41870-022-01105-6]
35. [35] H. Xu et al., "Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction", Journal of Circuits, Systems and Computers, vol. 32, no. 10, p. 2350175, 2023. [DOI:10.1142/S021812662350175X]
36. [36] K. Singh and S. Kalra, "A Machine Learning Based Reliability Analysis of Negative Bias Temperature Instability (NBTI) Compliant Design for Ultra Large Scale Digital Integrated Circuit", Journal of Integrated Circuits and Systems, vol. 18, no. 2, pp. 1-12, 2023. [DOI:10.29292/jics.v18i2.686]
37. [37] Z. Tang et al., "Semi-Supervised Transfer Learning Framework for Aging-Aware Library Characterization", IEEE Transactions on Circuits and Systems II: Express Briefs, 2023. [DOI:10.1109/TCSII.2023.3323384]
38. [38] M. T. H. Anik, H. I. Reefat, J.-L. Danger, S. Guilley, and N. Karimi, "Aging-Induced Failure Prognosis via Digital Sensors", UMBC Student Collection, 2023. [DOI:10.1145/3583781.3590204]
39. [39] L. Lu, J. Chen, M. Ulbricht, and M. Krstic, "Machine Learning Methodologies to Predict the Results of Simulation-Based Fault Injection", IEEE Transactions on Circuits and Systems I: Regular Papers, 2024. [DOI:10.1109/TCSI.2024.3349928]
40. [40] D. D. Gajski, N. D. Dutt, A. C. Wu, and S. Y. Lin, High-Level Synthesis: Introduction to Chip and System Design. Springer Science & Business Media, 2012.
41. [41] Y.-G. Chen, C. Lin, and Y.-C. Wei, "A novel NBTI-aware chip remaining lifetime prediction framework using machine learning", in 2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, pp. 476-481: IEEE. [DOI:10.1109/ISQED51717.2021.9424356]
42. [42] J. Brown et al., "A Pragmatic Model to Predict Future Device Aging", IEEE Access, 2023. [DOI:10.1109/ACCESS.2023.3329077]
43. [43] S. Tan, M. Tahoori, T. Kim, S. Wang, Z. Sun, and S. Kiamehr, "Long-term reliability of nanometer VLSI systems", Cham: Springer, 2019. [DOI:10.1007/978-3-030-26172-6]
44. [44] J. Franco et al., "Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs", in 2012 IEEE International Reliability Physics Symposium (IRPS), 2012, pp. 5A. 4.1-5A. 4.6: IEEE. [DOI:10.1109/IRPS.2012.6241841]
45. [45] H. Kukner et al., "NBTI aging on 32-bit adders in the downscaling planar FET technology nodes", in 2014 17th Euromicro Conference on Digital System Design, 2014, pp. 98-107: IEEE. [DOI:10.1109/DSD.2014.82]
46. [46] J. Hu, C. Yan, C. Guo, R. Jiang, D. Zhou, and X. Zeng, "A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits", in 2021 IEEE 14th International Conference on ASIC (ASICON), 2021, pp. 1-4: IEEE. [DOI:10.1109/ASICON52560.2021.9620392]
47. [47] Z. Zhang et al., "Aging-aware gate-level modeling for circuit reliability analysis", IEEE Transactions on Electron Devices, vol. 68, no. 9, pp. 4201-4207, 2021. [DOI:10.1109/TED.2021.3096171]
48. [48] S. Esshaghi, M. Bazli, and A. Esshaghi, "A Machine Learning-based Model for predicting Stochastic BTI Effects", Signal Processing and Renewable Energy, vol. 5, no. 4, pp. 67-81, 2021.
49. [49] https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design/library-characterization/liberate-trio-characterization-suite.html.
50. [50] H. Qin and Y. Ye, "Algorithms of the Möbius function by random forests and neural networks", Journal of big data, vol. 11, no. 1, p. 31, 2024. [DOI:10.1186/s40537-024-00889-7]
51. [51] "Open-Cell Library", www.si2.org. https://si2.org/open-cell-library/
52. [52] "sklearn.ensemble.RandomForestRegressor", scikit-learn.http://scikit-learn.org/stable/modules/generated/ sklearn.ensemble.RandomForestRegressor.html
53. [53] "Design Compiler", Synopsys | EDA Tools, Semiconductor IP and Application Security Solutions. https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra.html
54. [54] "ModelSim HDL simulator", Siemens Digital Industries Software https://eda.sw.siemens.com/en-US/ic/modelsim/.
55. [55] "Gold Standard in Static Timing Analysis - PrimeTime", Synopsys | EDA Tools, Semiconductor IP and Application Security Solutions. https://www.synopsys.com/ implementation-and-signoff/signoff/primetime.html.
56. [56] https://www.cbl.ncsu.edu/.

Add your comments about this article : Your username or Email:
CAPTCHA

Send email to the article author


Rights and permissions
Creative Commons License This Journal is an open access Journal Licensed under the Creative Commons Attribution-NonCommercial 4.0 International License. (CC BY NC 4.0)

© 2025 CC BY-NC 4.0 | Journal of Iranian Association of Electrical and Electronics Engineers

Designed & Developed by : Yektaweb