Volume 22, Issue 1 (JIAEEE Vol.22 No.1 2024)
Journal of Iranian Association of Electrical and Electronics Engineers 2024, 22(1): 0-0 |
Back to browse issues page
Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
Dadkhah A, Daghighi A, Hatami V, Mohammadi E. Effect of Source/Drain Implantation on Channel Resistance in DI SOD MOSFET. Journal of Iranian Association of Electrical and Electronics Engineers 2024; 22 (1)
URL: http://jiaeee.com/article-1-1700-en.html
URL: http://jiaeee.com/article-1-1700-en.html
Shahrekord University
Abstract: (403 Views)
In this paper, a comprehensive investigation and simulation of the source/drain (S/D) resistance (Rsd) in 22 nm channel length double-insulating (DI) silicon-on-diamond (SOD) metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. For the first time, the effect of the S/D ion implantation region with different dimensions on Rsd is thoroughly investigated and simulated. Simulation results demonstrate that Rsd is significantly affected by the dimensions and type of the S/D ion implantation region. Optimizing the dimensions and type of the S/D region can reduce Rsd by up to 5 times. This study reveals that employing a properly designed S/D region can considerably reduce Rsd in 22 nm channel length DI-SOD MOSFETs. This can lead to improved performance and efficiency of these transistors in various electronic applications.
Keywords: Double-insulated silicon-on-diamond MOSFETs, Source/drain resistance, Silicon-on-insulator MOSFET, MOSFET, Silicon-on-Diamond
Send email to the article author
| Rights and permissions | |
 |
This Journal is an open access Journal Licensed under the Creative Commons Attribution-NonCommercial 4.0 International License. (CC BY NC 4.0) |
