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In this paper, a digital calibration technique is presented to correct the effect of circuit non-idealities in pipelined analog-to-digital converters (ADCs). This method consists of two parts. Firstly, the circuit errors are roughly estimated with a background calibration scheme. Then, in the second part, the estimated errors are finely adjusted to follow the process and temperarure variations. In the proposed calibration method, a combination of equalization, comparator threshold voltage adjustment and histogram of decision poinits techniques along with the geometrical transfer characteristics of the backend ADC on the errors are utilized. The proposed calibration scheme is utilized in a 12-bit, 100 MS/s pipelined ADC with 12 1.5 bit/stage with capacitor non-flip-around (CNFA) struture and 2-bit backend flash ADC. The circuit level simulated values of signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) are improved about 31 dB and 41 dB, respectively, compared to the non-calibrated ADC.            

Keywords: Pipeline analog-to-digital converters, digital background calibration, gain error and nonlinearity.

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