Volume 22, Issue 1 (JIAEEE Vol.22 No.1 2025)
Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(1): 57-64 |
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Eskandari H, Daghighi A, Shafaghat E. Simulation of CMOS Fabrication Processes for Double-Insulating Silicon-on-Diamond MOSFET. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (1) :57-64
URL: http://jiaeee.com/article-1-1708-en.html
URL: http://jiaeee.com/article-1-1708-en.html
Shahrekord University
Abstract: (702 Views)
In this article, for the first time, simulation of CMOS fabrication processes for double-insulating silicon-on-diamond MOSFET is discussed. The fabrication process suitable for 22-nanometer feature size and the presence of two main insulating layers, are implemented according to the standard steps of CMOS processes. The diamond layer, as the first electrical insulator, has high thermal conductivity, which enables the application of this structure for high power and cryogenic operation. Due to the presence of silicon dioxide as the second electrical insulator, some of the main electrical characteristics of the transistor, such as threshold voltage, unity-gain cut-off frequency, on-current, and short channel effects are improved. Therefore, the threshold voltage of 0.225 V, on-current as 0.045 mA/um and unity-gain cut-off frequency of 370 GHz was extracted. The simulation results demonstrate the superiority of the structure compared with conventional silicon-on-insulator technologies of semiconductor devices.
Keywords: Simulation of Fabrication Process, Silicon-on-Diamond Transistor, Silicone on double layer insulation, CMOS standard processes, MOSFET
Type of Article: Research |
Subject:
Electronic
Received: 2024/03/18 | Accepted: 2024/07/29 | Published: 2025/05/29
Received: 2024/03/18 | Accepted: 2024/07/29 | Published: 2025/05/29
Extended Abstract [PDF 222 KB] (5 Download)
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