Volume 22, Issue 1 (JIAEEE Vol.22 No.1 2025)
Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(1): 49-55 |
Back to browse issues page
Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:
Dadkhah A, Daghighi A, Hatami V, Mohammadi E. Effect of Source/Drain Implantation on Channel Resistance in DI SOD MOSFET. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (1) :49-55
URL: http://jiaeee.com/article-1-1700-en.html
URL: http://jiaeee.com/article-1-1700-en.html
Shahrekord University
Abstract: (717 Views)
In this paper, a comprehensive investigation and simulation of the source/drain (S/D) resistance (Rsd) in 22 nm channel length double-insulating (DI) silicon-on-diamond (SOD) metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. For the first time, the effect of the S/D ion implantation region with different dimensions on Rsd is thoroughly investigated and simulated. Simulation results demonstrate that Rsd is significantly affected by the dimensions and type of the S/D ion implantation region. Optimizing the dimensions and type of the S/D region can reduce Rsd by up to 5 times. This study reveals that employing a properly designed S/D region can considerably reduce Rsd in 22 nm channel length DI-SOD MOSFETs. This can lead to improved performance and efficiency of these transistors in various electronic applications.
Keywords: Double-insulated silicon-on-diamond MOSFETs, Source/drain resistance, Silicon-on-insulator MOSFET, MOSFET, Silicon-on-Diamond
Type of Article: Research |
Subject:
Electronic
Received: 2024/02/24 | Accepted: 2024/06/25 | Published: 2025/05/29
Received: 2024/02/24 | Accepted: 2024/06/25 | Published: 2025/05/29
Extended Abstract [PDF 188 KB] (4 Download)
References
1. Ahopelto, J., et al., NanoElectronics roadmap for Europe: From nanodevices and innovative materials to system integration. Solid-State Electronics, 2019. 155: p. 7-19. [DOI:10.1016/j.sse.2019.03.014]
2. Carter, R., et al. 22nm FD SOI technology for emerging mobile, Internet-of-Things, and RF applications. in 2016 IEEE International Electron Devices Meeting (IEDM). 2016. IEEE.
3. Goswami., R. and R. Saha, Contemporary Trends in Semiconductor Devices. 2022: Springer. [DOI:10.1007/978-981-16-9124-9]
4. Mazellier, J.-P., et al. First demonstration of heat dissipation improvement in CMOS technology using Silicon-On-Diamond (SOD) substrates. in 2009 IEEE International SOI Conference. 2009. IEEE. [DOI:10.1109/SOI.2009.5318735]
5. Zhu, W., G. Zheng, S. Cao, and H. He, Thermal conductivity of amorphous SiO2 thin film: A molecular dynamics study. Scientific reports, 2018. 8(1): p. 10537. [DOI:10.1038/s41598-018-28925-6]
6. Makovejev, S., et al., Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI. Solid-State Electronics, 2016. 115: p. 219-224. [DOI:10.1016/j.sse.2015.08.022]
7. Halder, A., et al., Heat sink implementation in back-end of line for self-heating reduction in 22 nm FDSOI MOSFETs. Solid-State Electronics, 2021. 184: p. 108088. [DOI:10.1016/j.sse.2021.108088]
8. Rabarot, M., et al., Silicon-On-Diamond layer integration by wafer bonding technology. Diamond and related materials, 2010. 19(7-9): p. 796-805. [DOI:10.1016/j.diamond.2010.01.049]
9. Raleva, K., D. Vasileska, and S.M. Goodnick, Is SOD technology the solution to heating problems in SOI devices', IEEE Electron Device Letters, 2008. 29(6): p. 621-624. [DOI:10.1109/LED.2008.920756]
10. Dadkhah A. and A. Daghighi, A Novel Capacitance Model to Compute Front- and Back-Gate Threshold Voltage of Double Insulating Silicon-on-Diamond MOSFET, Journal of Iranian Association of Electrical and Electronics Engineers, 2024. 21 (1) : pp. 39-45. [DOI:10.61186/jiaeee.21.1.39]
11. Daghighi, A., A novel structure to improve DIBL in fully-depleted silicon-on-diamond substrate. Diamond and related materials, 2013. 40: p. 51-55. [DOI:10.1016/j.diamond.2013.10.010]
12. Daghighi, A., Double insulating silicon on diamond device. 2015, Google Patents.
13. Daghighi, A. and A. Dadkhah, A capacitance model for threshold voltage computation of double-insulating fully-depleted silicon-on-diamond MOSFET. The European Physical Journal Plus, 2023. 138(12): p. 1-10. [DOI:10.1140/epjp/s13360-023-04758-9]
14. Tasker, P.J. and B. Hughes, Importance of source and drain resistance to the maximum f/sub T/of millimeter-wave MODFETs. IEEE Electron Device Letters, 1989. 10(7): p. 291-293. [DOI:10.1109/55.29656]
15. Hoseini, Z. and A. Daghighi, Investigation and simulation of the effect of substrate doping on the switching delay of 22 nm Double-
Send email to the article author
| Rights and permissions | |
 |
This Journal is an open access Journal Licensed under the Creative Commons Attribution-NonCommercial 4.0 International License. (CC BY NC 4.0) |
