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This paper proposes a new structure for digital address decoders based on flip-flops with application in wake-up signal generators of wireless networks nodes. Such nodes equipped with this device can be utilized in Internet of Things applications where the nodes are dependent on environment energy harvesting to survive for a long time. Different parts in these wireless nodes should have an electrical circuit design with low energy consumption and our proposed address decoder used in the wake-up signal receiver can improve such systems. The proposed structure as a digital address decoder uses power much less than conventional digital address decoders. We showed that our device consumes power even more efficiently in systems with longer address lengths and higher input data rates. To reduce power consumption, the proposed structure uses a sequential architecture, comparator blocks, activation units and sleep mode design for flip-flops. Flip-flops' propagation delay is used to calculate the circuit total response delay which was conversely related to the power consumption of the design. Static power of the device was limited by determining the essential active MOSFETs of the whole design and putting the others in the sleep mode. Simulation of the both proposed and conventional structures were carried out in a 32nm Cmos library in Hspice and showed that for a structure with an address length of 64 bits and 100 kbps input data rate, we will have more than 90% reduction in power consumption compared to the state-of-the-art structures. Comparing the results with similar tasks and adding a telecommunication receiver segment promises a 50% reduction in the total power consumption of the wake-up receiver of a complete IOT device.
 

Keywords: Address decoder, Internet of Things, Wake-up signal generator, Dynamic power, Hspice

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