Volume 22, Issue 1 (JIAEEE Vol.22 No.1 2025)                   Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(1): 19-26 | Back to browse issues page


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Barpour M, Rajabpour Moghadam K, Mohamadi Khalilabad P. Fully Integrated Fractional-N Frequency Synthesizer in 180-nm CMOS Technology for ISM-Band frequency. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (1) :19-26
URL: http://jiaeee.com/article-1-1619-en.html
Department of Electrical Engineering, Bojnourd Branch, Islamic Azad University
Abstract:   (174 Views)
This paper presents a fully integrated fractional-N frequency synthesizer for ISM frequency band. In this paper a new linearization technique is presented for Charge Pump (CP) circuit that leads to enhance CP’s linearity and overall frequency synthesizer. The presented frequency synthesizer is implemented in 180-nm CMOS technology by using cadence-virtuoso cad tool. Simulation result of the proposed technique shows that the matching characterization of the CP enhanced by role of 44% and the maximum mismatch in the range of 0.2-1.6 V of control voltage is equal to 0.4 µA. The presented CP improves 25 dBc/Hz close-in phase noise of the overall synthesizer that eventually improved the receiver sensitivity. Simulation results of the overall frequency synthesizer demonstrated that the loop is locked in 2 µS, the phase noise in 1 KHz, 10 KHz, 100 KHz, and 1 MHz offsets are equal to -63 dBc/Hz, -90 dBc/Hz, -95 dBc/Hz, and -107 dBc/Hz, respectively, and the higher fractional-N spurs is 53 dBc below than carrier signal. Power dissipation of the presented frequency from a 1.8 V power supply is 1 mW.
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Type of Article: Research | Subject: Electronic
Received: 2023/08/1 | Accepted: 2024/06/1 | Published: 2025/05/29

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