A new structure is presented for digital delta-sigma modulator (DDSM). Novel architecture decreases hardware consumption, output quantization noise and spurs in Comparison to previous architectures. In order to reduce the delay, power consumption and increase maximum working frequency, the pipelining technique and the carry skip adder are used. Simulation proposed architecture shows that the quantization noise is declined as 15dB compared to 13-bit conventional third-order modulator. Furthermore, the results of digital implementation report significant reduction in the hardware consumption, the power consumption and increase 3 times in the maximum working frequency.

Keywords: Delta-sigma modulator, Nested architecture, Quantization noise, Spur, Pipelined adder, Carry skip adder, Fractional frequency synthesizer

Full-Text [PDF 1304 kb]   (949 Downloads)