Volume 14, Issue 4 (JIAEEE Vol.14 No.4 2018)                   Journal of Iranian Association of Electrical and Electronics Engineers 2018, 14(4): 41-54 | Back to browse issues page

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Fattah G, Masoumi N. Comprehensive Evaluation of Crosstalk and Delay Profiles in VLSI Interconnect Structures with Partially Coupled Lines. Journal of Iranian Association of Electrical and Electronics Engineers. 2018; 14 (4) :41-54
URL: http://jiaeee.com/article-1-459-en.html
Abstract:   (725 Views)
In this paper, we present a methodology to explore and evaluate the crosstalk noise and the profile of its variations, and the delay of interconnects through investigation of two groups of interconnect structures in nano scale VLSI circuits. The interconnect structures in the first group are considered to be partially coupled identical lines. In this case, by choosing proper values for different parameters, the crosstalk noise, when the victim line stays ahead of the aggressor line can be reduced up to 92% in comparison to when it is behind the aggressor line. The second group consists of a victim line shorter than the aggressor line. In this case, if the parameters are properly optimized, when the victim line is placed at the end of the aggressor line, the crosstalk noise can be reduced up to 86% in comparison to the case when the victim line is placed at the beginning.
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Type of Article: Research | Subject: Electronic
Received: 2017/11/28 | Accepted: 2017/11/28 | Published: 2017/11/28

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