Showing 2 results for Silicon-on-Diamond Mosfet
Afshin Dadkhah, Dr. Arash Daghighi,
Volume 21, Issue 1 (3-2024)
Abstract
In this paper, for the first time, a capacitive model near threshold voltage of Ultra-Thin-Body (UTB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET is extracted. The model is applicable in computations of front- and back-gate threshold voltage of 22 nm UTB DI SOD MOSFET for low drain voltages. The transistor has a second insulating layer on top of first insulating layer of conventional SOD MOSFET which partially covers the diamond layer. The device simulation results of the front- and back-gate threshold voltages and the extracted model threshold voltages in terms of gate oxide thickness, silicon film layer thickness, first and second insulating layer thicknesses are compared. The comparison with the model computed results and the device simulation outcomes are promising. The model physical findings present insight on the device parameters that directly influence the threshold voltages.
Afshin Dadkhah, Dr. Arash Daghighi, Vahid Hatami, Erfan Mohammadi,
Volume 22, Issue 1 (4-2025)
Abstract
In this paper, a comprehensive investigation and simulation of the source/drain (S/D) resistance (Rsd) in 22 nm channel length double-insulating (DI) silicon-on-diamond (SOD) metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. For the first time, the effect of the S/D ion implantation region with different dimensions on Rsd is thoroughly investigated and simulated. Simulation results demonstrate that Rsd is significantly affected by the dimensions and type of the S/D ion implantation region. Optimizing the dimensions and type of the S/D region can reduce Rsd by up to 5 times. This study reveals that employing a properly designed S/D region can considerably reduce Rsd in 22 nm channel length DI-SOD MOSFETs. This can lead to improved performance and efficiency of these transistors in various electronic applications.
