Mr. M. Abedi, Dr. J. Yavand Hasani,
Volume 14, Issue 2 (9-2017)
Abstract
In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in the circuit is based on Aperture Phase Detection (APD) method. In addition, the proposed charge pump reduces reference spur. The proposed structure of the frequency locked loop reduces the locking time. To evaluate the proposed approch, we simulated the designed PLL using the foundry design kit for 0.18μm CMOS technology. The spur level and lock time of the proposed circuit is -74dBc and 1.9 μs, respectively, implying 5dB improvement in spur level and 32% improvement in lock time compared with the previously proposed circuits. The power consumption of the proposed circuit is 4.15 mW.
Sr. Mohammadreza Barpour, Dr. Khosro Rajabpour Moghadam, Dr. Peyman Mohamadi Khalilabad,
Volume 22, Issue 1 (4-2025)
Abstract
This paper presents a fully integrated fractional-N frequency synthesizer for ISM frequency band. In this paper a new linearization technique is presented for Charge Pump (CP) circuit that leads to enhance CP’s linearity and overall frequency synthesizer. The presented frequency synthesizer is implemented in 180-nm CMOS technology by using cadence-virtuoso cad tool. Simulation result of the proposed technique shows that the matching characterization of the CP enhanced by role of 44% and the maximum mismatch in the range of 0.2-1.6 V of control voltage is equal to 0.4 µA. The presented CP improves 25 dBc/Hz close-in phase noise of the overall synthesizer that eventually improved the receiver sensitivity. Simulation results of the overall frequency synthesizer demonstrated that the loop is locked in 2 µS, the phase noise in 1 KHz, 10 KHz, 100 KHz, and 1 MHz offsets are equal to -63 dBc/Hz, -90 dBc/Hz, -95 dBc/Hz, and -107 dBc/Hz, respectively, and the higher fractional-N spurs is 53 dBc below than carrier signal. Power dissipation of the presented frequency from a 1.8 V power supply is 1 mW.
