Mr Afshin Dadkhah, Arash Daghighi, Vahid Hatami, Erfan Mohammadi,
Volume 22, Issue 1 (12-2024)
Abstract
In this paper, a comprehensive investigation and simulation of the source/drain (S/D) resistance (Rsd) in 22 nm channel length double-insulating (DI) silicon-on-diamond (SOD) metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. For the first time, the effect of the S/D ion implantation region with different dimensions on Rsd is thoroughly investigated and simulated. Simulation results demonstrate that Rsd is significantly affected by the dimensions and type of the S/D ion implantation region. Optimizing the dimensions and type of the S/D region can reduce Rsd by up to 5 times. This study reveals that employing a properly designed S/D region can considerably reduce Rsd in 22 nm channel length DI-SOD MOSFETs. This can lead to improved performance and efficiency of these transistors in various electronic applications.
