English title

Lock and settling times are two parameters which are of high importance in design of DLL-based frequency multipliers. A new architecture for DLL-based frequency multipliers in digital domain is designed in this paper. In the proposed architecture instead of using charge pump, phase frequency detector and loop filter a digital signal processor is used. Gradient algorithm is used in the proposed circuit to improve the DLLs parameter. The architecture can be easily implemented by simple digital signal processor (even with analog circuits). Also, simulations are provided in a case of 11 delay cells and input frequency of 300MHz. The simulation results show that the output frequency is 11 times of reference frequency (3.3 GHz) and lock time is equal to 17ns (5 cycles of reference clock). The simulation results confirm the analytical predictions

Reducing the locking time or settling time is one of the major challenges in the design of Delay Locked Loop (DLL) based frequency synthesizer. In this paper a common structure for DLL based frequency synthesizer is considered in which the number of delay cells in the direct path is specified. Then, the designed delay locked loop is optimized using genetic algorithm (GA). GA changes the phase-voltage gain coefficients of the delay cells for achieving the best locking (settling) time.  Typical DLL with a reference frequency of 100 MHz and 8 delay cells is studied. Simulation results is shown the proposed structure is locked in 0.58 mu.

In this paper, a new approach using gradient optimization algorithm for delay locked loop (DLL) is provided. Among the salient features of this structure, the proposed DLL can be quickly locked and can be used as a high-frequency circuit. In this novel architecture a digital signal processor (DSP) is used instead of phase detector, charge pump and loop filter. In digital transmitters to select kind of modulation, coding, decoding and…a DSP is used. Therefore, this DSP can be used in the proposed structure too. The proposed digital DLL has lower complexity than conventional analog DLLs. The structure is simulated using MATLAB for Bluetooth application. Five delay cells are used in the proposed digital DLL to generate 2.4GHz output frequency from 480MHz input frequency. The simulations confirm the high accuracy and speed of proposed digital DLL.