Volume 22, Issue 2 (JIAEEE Vol.22 No.2 2025)
Journal of Iranian Association of Electrical and Electronics Engineers 2025, 22(2): 0-0 |
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ersali salehi nasab M, seydi S. Modeling DRAM Access Based on Efficient Tiling in CNN Hardware Accelerators. Journal of Iranian Association of Electrical and Electronics Engineers 2025; 22 (2)
URL: http://jiaeee.com/article-1-1773-en.html
URL: http://jiaeee.com/article-1-1773-en.html
Tehran University
Abstract: (171 Views)
Artificial neural networks are a subset of machine learning inspired by the biological neural networks of the human brain and have the capability to learn. These networks are applied in various fields, including natural language processing, pattern recognition, image processing, computer vision, and many other areas. CNNs (Convolutional Neural Networks) are an example of these networks that have a layered structure, with convolution being their main operation. Due to the high volume of computations and the flow of data in these networks, there is an increased need for bandwidth and memory transfers. Recent researches have shown that the energy consumption and access time of external memory are 200x and 10x greater than internal memory respectively, which leads to increased energy consumption and an imbalance in the data path topology.
One of the main solutions to reduce energy consumption is to increase data reuse and reduce the number of accesses to external memory. Maximizing data usage reduces the number of data movements and memory accesses. One method for data reuse is loop-level scheduling and applying tiling techniques. This paper models the relationship between the number of accesses to external memory when using tiling. This model is presented as a mathematical formula that can determine the exact number of DRAM accesses based on network parameters and the tile size. Then, in an optimization problem, optimal parameters are obtained with the goal of minimizing the use of external memory and establishing the relationship between network configuration parameters and tile size.
One of the main solutions to reduce energy consumption is to increase data reuse and reduce the number of accesses to external memory. Maximizing data usage reduces the number of data movements and memory accesses. One method for data reuse is loop-level scheduling and applying tiling techniques. This paper models the relationship between the number of accesses to external memory when using tiling. This model is presented as a mathematical formula that can determine the exact number of DRAM accesses based on network parameters and the tile size. Then, in an optimization problem, optimal parameters are obtained with the goal of minimizing the use of external memory and establishing the relationship between network configuration parameters and tile size.
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