English title

Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. Supporting the highest bandwidth data rates among devices requires advanced clock management technology such as delay-locked loops (DLLs). The DLL circuitry allows for very precise synchronization of external and internal clocks. In this paper a low jitter and wide operation range Mixed-Mode Delay Locked Loop is presented. A multiperiod-locked technique is used to enhance the input frequency Range. Moreover, a new CP is proposed to suppress mismatch problem in single ended CPs. In this way jitter and static phase error specifications have been improved. The designed circuit has been simulated in ADS software, using TSMC 0.18 um CMOS process at 1.8V supply voltage. Simulation results show that the frequency range of the suggested DLL is from 170 to 1100 MHz. The rms jitter and power dissipation of the designed circuit at 1100 MHz are 3.3 psec and 4.554 mW, respectively.