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:: Volume 14, Issue 2 (Vol.14 No.2 2017) ::
Journal of Iranian Association of Electrical and Electronics Engineers 2017, 14(2): 87-96 Back to browse issues page
A Dual-Loop PLL Based on Aperture-Phase Detection, with Short Locking Time, Low Power, and Low Spur
M. Abedi Mr. , J. Yavand Hasani Dr.
Abstract:   (196 Views)
In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in the circuit is based on Aperture Phase Detection (APD) method. In addition, the proposed charge pump reduces reference spur. The proposed structure of the frequency locked loop reduces the locking time. To evaluate the proposed approch, we simulated the designed PLL using the foundry design kit for 0.18μm CMOS technology.  The spur level and lock time of the proposed circuit is -74dBc and  1.9 μs, respectively, implying 5dB improvement in spur level and 32% improvement in lock time compared with the previously proposed circuits. The power consumption of the proposed circuit is 4.15 mW.  
 
Keywords: Phase Locked Loop, Locking Time, Reference Spur, Aperture Phase Detector, Charge Pump, Frequency Divider, VCO
Full-Text [PDF 928 kb]   (92 Downloads)    
Type of Article: Research | Subject: Electronic
Received: 2017/09/4 | Accepted: 2017/09/4 | Published: 2017/09/4
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Abedi M, Yavand Hasani J. A Dual-Loop PLL Based on Aperture-Phase Detection, with Short Locking Time, Low Power, and Low Spur . Journal of Iranian Association of Electrical and Electronics Engineers. 2017; 14 (2) :87-96
URL: http://jiaeee.com/article-1-391-en.html
Volume 14, Issue 2 (Vol.14 No.2 2017) Back to browse issues page
نشریه مهندسی برق و الکترونیک ایران Journal of Iranian Association of Electrical and Electronics Engineers
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