XML Persian Abstract Print


Download citation:
BibTeX | RIS | EndNote | Medlars | ProCite | Reference Manager | RefWorks
Send citation to:

Gholami M, Rahimpour H, Ghasemi J, Esmaeili I. Design of Delay locked loop for Wireless Receivers to Use in High Frequency Applications. Journal of Iranian Association of Electrical and Electronics Engineers. 2017; 13 (4) :15-22
URL: http://jiaeee.com/article-1-41-en.html
Abstract:   (4337 Views)

In this paper, a new approach using gradient optimization algorithm for delay locked loop (DLL) is provided. Among the salient features of this structure, the proposed DLL can be quickly locked and can be used as a high-frequency circuit. In this novel architecture a digital signal processor (DSP) is used instead of phase detector, charge pump and loop filter. In digital transmitters to select kind of modulation, coding, decoding and…a DSP is used. Therefore, this DSP can be used in the proposed structure too. The proposed digital DLL has lower complexity than conventional analog DLLs. The structure is simulated using MATLAB for Bluetooth application. Five delay cells are used in the proposed digital DLL to generate 2.4GHz output frequency from 480MHz input frequency. The simulations confirm the high accuracy and speed of proposed digital DLL.

Full-Text [PDF 416 kb]   (1877 Downloads)    
Type of Article: Research | Subject: Communication
Received: 2017/01/17 | Accepted: 2017/01/17 | Published: 2017/01/17

Add your comments about this article : Your username or Email:
CAPTCHA

Send email to the article author


© 2021 All Rights Reserved | Journal of Iranian Association of Electrical and Electronics Engineers

Designed & Developed by : Yektaweb