Volume 21, Issue 1 (JIAEEE Vol.21 No.1 2024)
Journal of Iranian Association of Electrical and Electronics Engineers 2024, 21(1): 39-45 |
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Dadkhah A, Daghighi A. A Novel Capacitance Model to Compute Front- and Back-Gate Threshold Voltage of Double Insulating Silicon-on-Diamond MOSFET. Journal of Iranian Association of Electrical and Electronics Engineers 2024; 21 (1) :39-45
URL: http://jiaeee.com/article-1-1454-en.html
URL: http://jiaeee.com/article-1-1454-en.html
Faculty of Engineering, Shahrekord University, Shahrekord
Abstract: (867 Views)
In this paper, for the first time, a capacitive model near threshold voltage of Ultra-Thin-Body (UTB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET is extracted. The model is applicable in computations of front- and back-gate threshold voltage of 22 nm UTB DI SOD MOSFET for low drain voltages. The transistor has a second insulating layer on top of first insulating layer of conventional SOD MOSFET which partially covers the diamond layer. The device simulation results of the front- and back-gate threshold voltages and the extracted model threshold voltages in terms of gate oxide thickness, silicon film layer thickness, first and second insulating layer thicknesses are compared. The comparison with the model computed results and the device simulation outcomes are promising. The model physical findings present insight on the device parameters that directly influence the threshold voltages.
Keywords: Silicon-on-Insulator MOSFET, Silicon-on-Diamond MOSFET, Threshold Voltage, Capacitive Model, Double Insulating Silicon-on-Diamond MOSFET
Type of Article: Research |
Subject:
Electronic
Received: 2022/04/17 | Accepted: 2023/02/8 | Published: 2023/09/9
Received: 2022/04/17 | Accepted: 2023/02/8 | Published: 2023/09/9
Extended Abstract [PDF 370 KB] (12 Download)
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