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In this paper, a Dual-Bit Parallel Adder (DBPA) based on minority function using Carbon-Nanotube Field-Effect Transistor (CNFET) is proposed. The possibility of having several threshold voltage (V_t) levels by CNFETs leading to wide use of them in designing of digital circuits. The main goal of designing proposed DBPA is to reduce critical path delay in adder circuits. The proposed design positively effects the speed and power consumption parameters through data path shortening.  In order to evaluate the proposed design, several simulations are performed using Synopsys HSPICE in 32nmCMOS and 32nm CNFET technologies. Proposed DBPA circuit with five other two-bit adder circuits implemented using five different full adder cells in power consumption, delay and Power Delay Product (PDP) parameters has been compared. To evaluate the performance of different designs in larger circuits, 4-bit Ripple Carry Adder (RCA) and 8-bit RCA have been simulated. Based on obtained results, the proposed design is faster than other designs due to the data path shortening. The results of the simulations confirm the higher efficiency of the proposed design with respect to other designs.

Keywords: Dual Bit Parallel Adder, CNFET, Data path delay, Arithmetic circuits

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