English title

Lock and settling times are two parameters which are of high importance in design of DLL-based frequency multipliers. A new architecture for DLL-based frequency multipliers in digital domain is designed in this paper. In the proposed architecture instead of using charge pump, phase frequency detector and loop filter a digital signal processor is used. Gradient algorithm is used in the proposed circuit to improve the DLLs parameter. The architecture can be easily implemented by simple digital signal processor (even with analog circuits). Also, simulations are provided in a case of 11 delay cells and input frequency of 300MHz. The simulation results show that the output frequency is 11 times of reference frequency (3.3 GHz) and lock time is equal to 17ns (5 cycles of reference clock). The simulation results confirm the analytical predictions