<?xml version="1.0" encoding="utf-8"?>
<journal>
<title>Journal of Iranian Association of Electrical and Electronics Engineers</title>
<title_fa>نشریه مهندسی برق و الکترونیک ایران</title_fa>
<short_title>Journal of Iranian Association of Electrical and Electronics Engineers</short_title>
<subject>Engineering &amp; Technology</subject>
<web_url>http://jiaeee.com</web_url>
<journal_hbi_system_id>1</journal_hbi_system_id>
<journal_hbi_system_user>admin</journal_hbi_system_user>
<journal_id_issn>2676-5810</journal_id_issn>
<journal_id_issn_online>2676-6086</journal_id_issn_online>
<journal_id_pii>8</journal_id_pii>
<journal_id_doi>10.61882/jiaeee</journal_id_doi>
<journal_id_iranmedex></journal_id_iranmedex>
<journal_id_magiran></journal_id_magiran>
<journal_id_sid>14</journal_id_sid>
<journal_id_nlai>8888</journal_id_nlai>
<journal_id_science>13</journal_id_science>
<language>fa</language>
<pubdate>
	<type>jalali</type>
	<year>1397</year>
	<month>11</month>
	<day>1</day>
</pubdate>
<pubdate>
	<type>gregorian</type>
	<year>2019</year>
	<month>2</month>
	<day>1</day>
</pubdate>
<volume>15</volume>
<number>4</number>
<publish_type>online</publish_type>
<publish_edition>1</publish_edition>
<article_type>fulltext</article_type>
<articleset>
	<article>


	<language>en</language>
	<article_id_doi></article_id_doi>
	<title_fa>Multi Objective Inclined Planes System Optimization Algorithm for VLSI Circuit Partitioning</title_fa>
	<title>Multi Objective Inclined Planes System Optimization Algorithm for VLSI Circuit Partitioning</title>
	<subject_fa>الکترونیک</subject_fa>
	<subject>Electronic</subject>
	<content_type_fa>پژوهشي</content_type_fa>
	<content_type>Research</content_type>
	<abstract_fa>&lt;div dir=&quot;ltr&quot;&gt;&lt;span style=&quot;font-weight:normal;&quot;&gt;&lt;span style=&quot;font-size:10.0pt;&quot;&gt;In this paper multi objective optimization problem for partitioning process of VLSI circuit optimization is solved using IPO algorithm. The methodology used in this paper is based upon the &lt;/span&gt;&lt;/span&gt;&lt;span style=&quot;font-weight:normal;&quot;&gt;&lt;span style=&quot;font-size:10.0pt;&quot;&gt;dynamic of sliding motion along a frictionless inclined plane. &lt;/span&gt;&lt;/span&gt;&lt;span style=&quot;font-weight:normal;&quot;&gt;&lt;span style=&quot;font-size:10.0pt;&quot;&gt;In this work, modules and elements of the circuit are divided into two smaller parts (components) in order to minimize the cutsize and area imbalance&lt;/span&gt;&lt;/span&gt;&lt;span style=&quot;font-weight:normal;&quot;&gt;&lt;span style=&quot;font-size:10.0pt;&quot;&gt;. &lt;/span&gt;&lt;/span&gt;&lt;span style=&quot;font-weight:normal;&quot;&gt;&lt;span style=&quot;font-size:10.0pt;&quot;&gt;The algorithm is implemented to test real case study named RC6 block cipher circuit. The multi objective IPO algorithm (MOIPO) will give better results in comparison with the multi objective particle swarm optimization algorithm (MOPSO) with the same evaluation function.&lt;/span&gt;&lt;/span&gt;&lt;/div&gt;
</abstract_fa>
	<abstract>In this paper multi objective optimization problem for partitioning process of VLSI circuit optimization is solved using IPO algorithm. The methodology used in this paper is based upon the dynamic of sliding motion along a frictionless inclined plane. In this work, modules and elements of the circuit are divided into two smaller parts (components) in order to minimize the cutsize and area imbalance. The algorithm is implemented to test real case study named RC6 block cipher circuit. The multi objective IPO algorithm (MOIPO) will give better results in comparison with the multi objective particle swarm optimization algorithm (MOPSO) with the same evaluation function.</abstract>
	<keyword_fa>MOIPO, Optimization algorithm, Partitioning, Cutsize, Area imbalance.</keyword_fa>
	<keyword>MOIPO, Optimization algorithm, Partitioning, Cutsize, Area imbalance.</keyword>
	<start_page>137</start_page>
	<end_page>143</end_page>
	<web_url>http://jiaeee.com/browse.php?a_code=A-10-183-24&amp;slc_lang=en&amp;sid=1</web_url>


<author_list>
	<author>
	<first_name>Somayyeh </first_name>
	<middle_name></middle_name>
	<last_name>Hosseinzadeh</last_name>
	<suffix></suffix>
	<first_name_fa>سمیه</first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa>حسین زاده</last_name_fa>
	<suffix_fa></suffix_fa>
	<email>s.hosseinzadeh.70@gmail.com</email>
	<code>10031947532846003709</code>
	<orcid>10031947532846003709</orcid>
	<coreauthor>Yes
</coreauthor>
	<affiliation>Department of Electrical Engineering- University of Birjand Birjand- Iran</affiliation>
	<affiliation_fa>Department of Electrical Engineering- University of Birjand Birjand- Iran</affiliation_fa>
	 </author>


	<author>
	<first_name> Seyed Hamid</first_name>
	<middle_name></middle_name>
	<last_name> Zahiri</last_name>
	<suffix></suffix>
	<first_name_fa>سیدحمید</first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa>ظهیری</last_name_fa>
	<suffix_fa></suffix_fa>
	<email>hzahiri@birjand.ac.ir</email>
	<code>10031947532846003710</code>
	<orcid>10031947532846003710</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electrical Engineering- University of Birjand Birjand- Iran</affiliation>
	<affiliation_fa>Department of Electrical Engineering- University of Birjand Birjand- Iran</affiliation_fa>
	 </author>


</author_list>


	</article>
</articleset>
</journal>
