Volume 13, Issue 2 (7-2016)
Journal of Iranian Association of Electrical and Electronics Engineers 2016, 13(2): 133-140 |
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Ghasemi J, Gholami M. Study of the Optimal Coefficients for the Gain of Delay Line in DLL for Obtaining Low Settling Time. Journal of Iranian Association of Electrical and Electronics Engineers 2016; 13 (2) :133-140
URL: http://jiaeee.com/article-1-70-en.html
URL: http://jiaeee.com/article-1-70-en.html
Abstract: (4121 Views)
Reducing the locking time or settling time is one of the major challenges in the design of Delay Locked Loop (DLL) based frequency synthesizer. In this paper a common structure for DLL based frequency synthesizer is considered in which the number of delay cells in the direct path is specified. Then, the designed delay locked loop is optimized using genetic algorithm (GA). GA changes the phase-voltage gain coefficients of the delay cells for achieving the best locking (settling) time. Typical DLL with a reference frequency of 100 MHz and 8 delay cells is studied. Simulation results is shown the proposed structure is locked in 0.58 mu.
Type of Article: Research |
Subject:
Communication
Received: 2017/02/1 | Accepted: 2017/02/1 | Published: 2017/02/1
Received: 2017/02/1 | Accepted: 2017/02/1 | Published: 2017/02/1
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