Volume 18, Issue 4 (JIAEEE Vol.18 No.4 2021)
Journal of Iranian Association of Electrical and Electronics Engineers 2021, 18(4): 97-105 |
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Molaei H, Haj Sadeghi K. Design of Delay Element for Time to Digital Converters. Journal of Iranian Association of Electrical and Electronics Engineers 2021; 18 (4) :97-105
URL: http://jiaeee.com/article-1-683-en.html
URL: http://jiaeee.com/article-1-683-en.html
EE Department, Sharif University of Technology
Abstract: (1510 Views)
Design of the delay element, a key building block of the time to digital converters (TDCs), is a challenging part of the ADPLL design. Beside the analyzing different types of variable delay elements, a novel delay element design is proposed to minimize the propagation delay and increases resolution of the TDCs proportionally. In addition, sensitivity of the proposed design to mismatch and process variations is less than the conventional designs. To validate the effectiveness of the idea, a new 8bit TDC is designed which uses a tunable gain time amplifier (TA) and achieves the sub picosecond resolution. By utilizing a calibration circuit, the TA gain variation reduces to less than 1%. Simulation results in 0.18µm CMOS technology show 35% reduction in TDC resolution and some 20% improvement in power consumption.
Type of Article: Research |
Subject:
Electronic
Received: 2018/10/8 | Accepted: 2019/06/23 | Published: 2021/10/14
Received: 2018/10/8 | Accepted: 2019/06/23 | Published: 2021/10/14
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