<?xml version="1.0" encoding="utf-8"?>
<journal>
<title>Journal of Iranian Association of Electrical and Electronics Engineers</title>
<title_fa>نشریه مهندسی برق و الکترونیک ایران</title_fa>
<short_title>Journal of Iranian Association of Electrical and Electronics Engineers</short_title>
<subject>Engineering &amp; Technology</subject>
<web_url>http://jiaeee.com</web_url>
<journal_hbi_system_id>1</journal_hbi_system_id>
<journal_hbi_system_user>admin</journal_hbi_system_user>
<journal_id_issn>2676-5810</journal_id_issn>
<journal_id_issn_online>2676-6086</journal_id_issn_online>
<journal_id_pii>8</journal_id_pii>
<journal_id_doi>10.61882/jiaeee</journal_id_doi>
<journal_id_iranmedex></journal_id_iranmedex>
<journal_id_magiran></journal_id_magiran>
<journal_id_sid>14</journal_id_sid>
<journal_id_nlai>8888</journal_id_nlai>
<journal_id_science>13</journal_id_science>
<language>fa</language>
<pubdate>
	<type>jalali</type>
	<year>1396</year>
	<month>12</month>
	<day>1</day>
</pubdate>
<pubdate>
	<type>gregorian</type>
	<year>2018</year>
	<month>3</month>
	<day>1</day>
</pubdate>
<volume>14</volume>
<number>4</number>
<publish_type>online</publish_type>
<publish_edition>1</publish_edition>
<article_type>fulltext</article_type>
<articleset>
	<article>


	<language>en</language>
	<article_id_doi></article_id_doi>
	<title_fa>Comprehensive Evaluation of Crosstalk and Delay Profiles in VLSI Interconnect Structures with Partially Coupled Lines</title_fa>
	<title>Comprehensive Evaluation of Crosstalk and Delay Profiles in VLSI Interconnect Structures with Partially Coupled Lines</title>
	<subject_fa>الکترونیک</subject_fa>
	<subject>Electronic</subject>
	<content_type_fa>پژوهشي</content_type_fa>
	<content_type>Research</content_type>
	<abstract_fa>&lt;div dir=&quot;ltr&quot; style=&quot;text-align: justify;&quot;&gt;In this paper, we present a methodology to explore and evaluate the crosstalk noise and the profile of its variations, and the delay of interconnects through investigation of two groups of interconnect structures in nano scale VLSI circuits. The interconnect structures in the first group are considered to be partially coupled identical lines. In this case, by choosing proper values for different parameters, the crosstalk noise, when the victim line stays ahead of the aggressor line can be reduced up to 92% in comparison to when it is behind the aggressor line. The second group consists of a victim line shorter than the aggressor line. In this case, if the parameters are properly optimized, when the victim line is placed at the end of the aggressor line, the crosstalk noise can be reduced up to 86% in comparison to the case when the victim line is placed at the beginning.&lt;/div&gt;
</abstract_fa>
	<abstract>&lt;div style=&quot;text-align: justify;&quot;&gt;In this paper, we present a methodology to explore and evaluate the crosstalk noise and the profile of its variations, and the delay of interconnects through investigation of two groups of interconnect structures in nano scale VLSI circuits. The interconnect structures in the first group are considered to be partially coupled identical lines. In this case, by choosing proper values for different parameters, the crosstalk noise, when the victim line stays ahead of the aggressor line can be reduced up to 92% in comparison to when it is behind the aggressor line. The second group consists of a victim line shorter than the aggressor line. In this case, if the parameters are properly optimized, when the victim line is placed at the end of the aggressor line, the crosstalk noise can be reduced up to 86% in comparison to the case when the victim line is placed at the beginning.&lt;/div&gt;
</abstract>
	<keyword_fa>Interconnect, Crosstalk, partially coupled lines.</keyword_fa>
	<keyword>Interconnect, Crosstalk, partially coupled lines.</keyword>
	<start_page>41</start_page>
	<end_page>54</end_page>
	<web_url>http://jiaeee.com/browse.php?a_code=A-10-1-249&amp;slc_lang=en&amp;sid=1</web_url>


<author_list>
	<author>
	<first_name>Golnaz </first_name>
	<middle_name></middle_name>
	<last_name>Fattah</last_name>
	<suffix></suffix>
	<first_name_fa>Golnaz </first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa>Fattah</last_name_fa>
	<suffix_fa></suffix_fa>
	<email>gfattah.h@gmail.com</email>
	<code>10031947532846001837</code>
	<orcid>10031947532846001837</orcid>
	<coreauthor>Yes
</coreauthor>
	<affiliation></affiliation>
	<affiliation_fa>MSc Graduate, Research Assistant, School of Electrical and Computer Eng., College of Eng., University of Tehran</affiliation_fa>
	 </author>


	<author>
	<first_name>Nasser </first_name>
	<middle_name></middle_name>
	<last_name>Masoumi</last_name>
	<suffix></suffix>
	<first_name_fa>Nasser </first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa>Masoumi</last_name_fa>
	<suffix_fa></suffix_fa>
	<email>nmasoumi@ut.ac.ir</email>
	<code>10031947532846001838</code>
	<orcid>10031947532846001838</orcid>
	<coreauthor>No</coreauthor>
	<affiliation></affiliation>
	<affiliation_fa>Professor,School of Electrical and Computer Eng., College of Eng., University of Tehran</affiliation_fa>
	 </author>


</author_list>


	</article>
</articleset>
</journal>
