en A Broadband Low Power CMOS LNA for 3.1–10.6 GHz UWB Receivers الکترونیک Electronic پژوهشي Research <div dir="ltr" style="text-align: justify;"><span style="color:black;"><span style="font-family:times new roman,serif;"><span style="font-size:10.0pt;">A new approach for designing an ultra wideband (UWB) CMOS low noise amplifier (LNA) is presented. The aim of this design is to achieve a low noise figure, reasonable power gain and low power consumption in 3.1-10.6 GHz. Also, the figure of merit (FOM) is significantly improved at 180nm technology compared to the other state-of-the-art designs. Improved &pi;-network and T-network are used to obtain a high and smooth power gain for the whole frequency band. Impedance matching and noise matching are designed with double feedback and only one inductor that are used at the input of the LNA. Post layout simulation is done for design validation. In this design post layout simulations show the low noise figure of 3.85&plusmn;0.25 dB</span></span></span><span style="color:black;"><span style="font-family:times new roman,serif;"><span style="font-size:10.0pt;">, reasonable</span></span></span><span style="color:black;"><span style="font-family:times new roman,serif;"><span style="font-size:10.0pt;"> power gain (18.08dB) and input return loss less than -9.1dB in full band of UWB. The power consumption of the circuit is only 11.3mW from 1.8V voltage supply. The LNA has the group delay about 111&plusmn;43ps. An input third-order intermodulation point (IIP3) of -9.2 dBm is achieved at 4 GHz. The layout area is 1.056 &times; 0.658 mm².</span></span></span></div> <div style="text-align: justify;">A new approach for designing an ultra wideband (UWB) CMOS low noise amplifier (LNA) is presented. The aim of this design is to achieve a low noise figure, reasonable power gain and low power consumption in 3.1-10.6 GHz. Also, the figure of merit (FOM) is significantly improved at 180nm technology compared to the other state-of-the-art designs. Improved &pi;-network and T-network are used to obtain a high and smooth power gain for the whole frequency band. Impedance matching and noise matching are designed with double feedback and only one inductor that are used at the input of the LNA. Post layout simulation is done for design validation. In this design post layout simulations show the low noise figure of 3.85&plusmn;0.25 dB, reasonable power gain (18.08dB) and input return loss less than -9.1dB in full band of UWB. The power consumption of the circuit is only 11.3mW from 1.8V voltage supply. The LNA has the group delay about 111&plusmn;43ps. An input third-order intermodulation point (IIP3) of -9.2 dBm is achieved at 4 GHz. The layout area is 1.056 &times; 0.658 mm².</div> Ultra wideband, UWB, Low Noise Amplifier, LNA, CMOS. Ultra wideband, UWB, Low Noise Amplifier, LNA, CMOS. 1 13 http://jiaeee.com/browse.php?a_code=A-10-1-246&slc_lang=en&sid=1 Amir Farzad Khavari Amir Farzad Khavari amir.khavari@mail.um.ac.ir 10031947532846001830 10031947532846001830 Yes Ph.D. Candidate, Department of Electrical Engineering, Faculty of Engineering, Ferdowsi University, Mashhad, Iran Khalil Mafinezhad Khalil Mafinezhad khmafinezhad@gmail.com 10031947532846001831 10031947532846001831 No Full Professor, Department of Electrical Engineering, Sadjad University of Technology, Mashhad, Iran Mohammad Maymandi Nejad Mohammad Maymandi Nejad maymandi@um.ac.ir 10031947532846001832 10031947532846001832 No Associate Professor, Department of Electrical Engineering, Faculty of Engineering, Ferdowsi University, Mashhad, Iran