Journal of Iranian Association of Electrical and Electronics Engineers
مجله مهندسی برق و الکترونیک ایران
Journal of Iranian Association of Electrical and Electronics Engineers
Engineering & Technology
http://jiaeee.com
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admin
2676-5810
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jalali
1389
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gregorian
2010
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Design and Synthesis of High Speed Low Power
Signed Digit Adders
Design and Synthesis of High Speed Low Power Signed Digit Adders
الکترونیک
Electronic
پژوهشي
Research
<p>Signed digit (SD) number systems provide the possibility of constant-time addition, where inter-digit carry propagation<br>
is eliminated. Such carry-free addition is primarily a three-step process; adding the equally weighted SDs to form the<br>
primary sum digits, decomposing the latter to interim sum digits and transfer digits, which commonly belong to<br>
{–1, 0, 1}, and finally adding the transfers to the corresponding (i.e., with the same weight) interim sum digits. All the<br>
final sum digits are therefore obtained in parallel. The special case of radix-2h maximally redundant SD number systems<br>
is more attractive due to maximum symmetric range (i.e., [–2h+1, 2h–1]) with only one redundancy bit per SD, and the<br>
possibility of more efficient carry-free addition. The previous relevant works use three parallel adders that compute sum<br>
and sum±1, where some speed-up is gained at the cost of more area and power. In this paper, we propose an alternative<br>
nonspeculative addition scheme that uses carry-save encoding for representation of the primary sum and interim sum<br>
digits and computes the transfer digits via a fast combinational logic. The simulation and synthesis of the proposed<br>
adder, based on 0.13 μm CMOS technology, shows advantages in terms of speed, power and area.</p>
<p style="text-align: justify;">Signed digit (SD) number systems provide the possibility of constant-time addition, where inter-digit carry propagation<br>
is eliminated. Such carry-free addition is primarily a three-step process; adding the equally weighted SDs to form the<br>
primary sum digits, decomposing the latter to interim sum digits and transfer digits, which commonly belong to<br>
{–1, 0, 1}, and finally adding the transfers to the corresponding (i.e., with the same weight) interim sum digits. All the<br>
final sum digits are therefore obtained in parallel. The special case of radix-2h maximally redundant SD number systems<br>
is more attractive due to maximum symmetric range (i.e., [–2h+1, 2h–1]) with only one redundancy bit per SD, and the<br>
possibility of more efficient carry-free addition. The previous relevant works use three parallel adders that compute sum<br>
and sum±1, where some speed-up is gained at the cost of more area and power. In this paper, we propose an alternative<br>
nonspeculative addition scheme that uses carry-save encoding for representation of the primary sum and interim sum<br>
digits and computes the transfer digits via a fast combinational logic. The simulation and synthesis of the proposed<br>
adder, based on 0.13 μm CMOS technology, shows advantages in terms of speed, power and area.</p>
Computer arithmetic, Carry-free addition, Signed-digit number systems, Low power design, Maximal
redundancy.
Computer arithmetic, Carry-free addition, Signed-digit number systems, Low power design, Maximal
redundancy.
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