TY - JOUR T1 - New Coupled-Inductor Based Multilevel Inverter with Extension Capability TT - New Coupled-Inductor Based Multilevel Inverter with Extension Capability JF - jiaeee JO - jiaeee VL - 15 IS - 4 UR - http://jiaeee.com/article-1-797-en.html Y1 - 2019 SP - 61 EP - 71 KW - Multilevel inverter KW - coupled-inductor KW - high-current application. N2 - Multilevel inverters have been developed due to limitations of the conventional two-level voltage source inverters (VSIs). Most of the topologies of multilevel inverters that have been presented in the literature are based on the sharing of the rated voltage between the switches so that the switches with lower voltage ratings can be used. In these topologies, the current rating of all of the switches is equal to the rated output current. Therefore, they may have limitations in high-current application. Recently, the coupled-inductor based multilevel inverter topologies have been presented to overcome the mentioned problem. In these topologies, the current rating of the switches is lower than the rated output current. In other words, these topologies can increase output current in comparison with the switches current. In this paper, a new generalized coupled-inductor based multilevel inverter is presented. The proposed topology consists of various coupled cells and can be extended to any number of voltage levels. This gives the generality and design flexibility for the proposed topology. If cells are used in the proposed topology, the switches operate at the rated current equal to of the rated output current. This shows a considerable in the switches current ratings. The number of voltage levels can be increased so that switches with lower current ratings can be used and at the same time, the quality of output voltage and current improves considerably. For the proposed topology, the pulse width modulation (PWM) method is also presented. The simulation results of the proposed 9-level inverter (in both single-phase and three-phase conditions) are presented to demonstrate the performance of the proposed topology. M3 ER -