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This paper proposes the use of DTMOS transistors in a memristor-based ternary CAM (MTCAM) instead of MOSFET transistors. It also evaluates the effect of forward body biasing methods in DTMOS transistors on the performance of a MTCAM cell in write mode. These biasing methods are gate-to-body tying (called DT1), drain-to-body tying (called DT2), and gate-to-body tying with a voltage supply of 0.1 V (called DT3). The simulation results of DTMOS-based MTCAMs in comparison with a MOSFET-based MTCAM showed that the use of DT1 method enhances power dissipation and Power Delay Product (PDP) by 86% and 42%, respectively but increases the delay by 30%, the use of DT2 method enhances power dissipation and PDP by 87% and 60%, respectively but increases the delay by 20%, and the use of DT3 method enhances power dissipation and PDP by 89% and 74%, respectively but increases the delay by 14%. As a result, DT3-MTCAM has the least power and delay. Therefore, it is more suitable for low power applications. Simulations are performed in 40 MHz and 180 nm CMOS technology.

Keywords: CAM Memory, Ternary Logic, Memristor, DTMOS Transistor, Forward body bias, low power.

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