Volume 21, Issue 1 (JIAEEE Vol.21 No.1 2024)                   Journal of Iranian Association of Electrical and Electronics Engineers 2024, 21(1): 77-84 | Back to browse issues page

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Charoosaei M, Monfaredi K, Yousefi M. A LOW POWER DUAL-MODE Reconfigurable SIGMA-DELTA MODULATOR DESIGN FOR GSM / WCDMA STANDARDS. Journal of Iranian Association of Electrical and Electronics Engineers 2024; 21 (1) :77-84
URL: http://jiaeee.com/article-1-1394-en.html
A LOW POWER DUAL-MODE Reconfigurable SIGMA-DELTA MODULATOR DESIGN FOR GSM / WCDMA STANDARDS
Majeed Charoosaei , Khalil Monfaredi , Mousa Yousefi *
Azarbaijan Shahid Madani University
Abstract:   (830 Views)
This paper presents a cascaded 2-2 reconfigurable sigma-delta modulator that can handle GSM and WCDMA standards. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is turned on to achieve 83dB dynamic range with oversampling ratio of 160 for a bandwidth of 200 KHz ; in WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in both stage to achieve 65 dB dynamic range with oversampling ratio of 16 for a bandwidth of 2 MHz .The results show that power consumption of proposed modulator is lower than other counterparts. Modulator are simulated by Cadence software utilizing 180 nm TSMC technology and operates at 1.8 supply voltage.
Keywords: cascode sigma-delta modulator, dual mode, reconfigurable, GSM and WCDMA standards.
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Type of Article: Research | Subject: Electronic
Received: 2021/11/1 | Accepted: 2022/12/31 | Published: 2023/09/9
Extended Abstract [PDF 248 KB]  (12 Download)
References
1. [1] K. Monfaredi, Distributed unique-size MOS technique: a promising universal approach capable of resolving circuit design bottlenecks of modern era, Circuits, Systems, and Signal Processing, 38(2) (2019) 512-528. [DOI:10.1007/s00034-018-0888-3]
2. [2] J.A. Castillo, J.J.O. Hidalgo, I.V. Álvarez, Delta-Sigma Converter Processing: aplicacion de herramienta de software libre para el analisis y caracterizacion de convertidores ƒÃƒ', Pistas Educativas, 36(112) (2018).
3. [3] M.R. Farsi, K. Monfaredi, Design and simulation of high precision second-order sigma-delta modulator for bluetooth applications, Journal of Engineering Science and Technology, 13(10) (2018) 3071-3079.
4. [4] M. Farsi, K. Monfaredi, Design and Simulation of Second Order Sigma-Delta Modulator with Very High Precision and Low Power Consumption for Medical Applications, Journal of Modeling in Engineering, 16(55) (2018) 191-197.
5. [5] D. Sharma, R. Paily, Multi-standard Σ-Δ Modulator for GSM/WCDMA Applications, IETE Journal of Research, 58(4) (2012) 292-299. [DOI:10.4103/0377-2063.102308]
6. [6] B.M. Zaky, H.A. Omran, H.A. Elsayed, Reconfigurable Multi-Mode Sigma Delta Modulator for 5G Applications, in: 2021 38th National Radio Science Conference (NRSC), IEEE, 2021, pp. 223-231. [DOI:10.1109/NRSC52299.2021.9509784]
7. [7] A. Atac, Design of Low Power Reconfigurable Continuous Time Quadrature Bandpass ΔΣ ADCs for Multi-Standard SoC, Dissertation, Rheinisch-Westfälische Technische Hochschule Aachen, 2016, 2016.
8. [8] K. Monfaredi, S. Jan Mohammadi, Dynamic foreground calibration of binary-weighted current-steering DAC, Iranian Journal of Science and Technology, Transactions of Electrical Engineering, 43(4) (2019) 699-716. [DOI:10.1007/s40998-019-00198-3]
9. [9] K. Monfaredi, M. Yousefi, Distributed MOS Transistor Technique to Facilitate Dynamic Element Matching Implementation Capability in Low Power 10-Bit Binary Digital to Analog Converter, Journal of Iranian Association of Electrical and Electronics Engineers, (2022) 0-0.
10. [10] A. Suanes, M. Dei, L. Terés, F. Serra-Graells, A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs, Integration, 84 (2022) 159-170. [DOI:10.1016/j.vlsi.2022.02.002]
11. [11] R. del Rio, M. Jose, CMOS sigma-delta converters: Practical design guide, John Wiley & Sons, 2013.
12. [12] L. Zhang, V. Nadig, M. Ismail, A high order multi-bit/spl sigma//spl delta/modulator for multi-standard wireless receiver, in: The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS'04., IEEE, 2004, pp. iii-379.
13. [13] B.J. Farahani, M. Ismail, A low power multi-standard sigma-delta ADC for WCDMA/GSM/Bluetooth applications, in: The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004., IEEE, 2004, pp. 241-243.
14. [14] S.J. Azhari, K. Monfaredi, S. Amiri, A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV, International Nano Letters, 2(1) (2012) 1-7. [DOI:10.1186/2228-5326-2-35]
15. [15] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto, F. Maloberti, Modeling sigma-delta modulator non-idealities in SIMULINK (R), in: 1999 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 1999, pp. 384-387.
16. [16] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, A. Baschirotto, Behavioral modeling of switched-capacitor sigma-delta modulators, IEEE Transactions on Circuits and Systems I: Fundamental theory and applications, 50(3) (2003) 352-364. [DOI:10.1109/TCSI.2003.808892]
17. [17] R. Sebastian, T. Shahana, B.R. Jose, Cascaded sigma delta modulator architectures for wideband ADCs, Cochin University of Science and Technology, 2020.
18. [18] M. Farsi, K. Monfaredi, A low voltage recycling folded cascode OTA based on novel CMRR magnifier, Journal of Telecommunication, Electronic and Computer Engineering (JTEC), 10(4) (2018) 37-42.
19. [19] K. Monfaredi, H. Faraji Baghtash, An extremely low-voltage and high-compliance current mirror, Circuits, Systems, and Signal Processing, 39(1) (2020) 30-53. [DOI:10.1007/s00034-019-01175-1]
20. [20] M.T. Nguyen, C. Jabbour, C. Ouffoue, R. Mina, F. Sibille, P. Loumeau, P. Triaire, Direct delta-sigma receiver: Analysis, modelization and simulation, in: 2013 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2013, pp. 1035-1038.
21. [21] K. Monfaredi, Y. Belghisazar, Improved low voltage low power recycling folded fully differential cascode amplifier, TABRIZ Journal of electrical Engineering, 48(1) (2018) 327-334.
22. [22] A. Fazli Yeknami, A. Alvandpour, A 2.1 μW 80 dB SNR DT ΔΣ modulator for medical implant devices in 65 nm CMOS, Analog Integrated Circuits and Signal Processing, 77(1) (2013) 69-78. [DOI:10.1007/s10470-013-0087-x]
23. [23] J. Jarvinen, K. Halonen, A 1.2 V Dual-Mode GSM/WCDMA-Modulator in 65nm CMOS, in: 2006 IEEE International Solid State Circuits Conference-Digest of Technical Papers, IEEE, 2006, pp. 1972-1981. [DOI:10.1109/ISSCC.2006.1696255]
24. [24] T. Christen, Q. Huang, A 0.13 µm CMOS 0.1-20MHz bandwidth 86-70dB DR multi-mode DT ΔΣ ADC for IMT-Advanced, in: 2010 Proceedings of ESSCIRC, IEEE, 2010, pp. 414-417.
25. [25] M. Honarparvar, E.N. Aghdam, M. Shamsi, A. Zahedi, M. Zafaranchi, A low power, high performance multi-mode delta-sigma ADC for GSM, WCDMA and WLAN standards, in: 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA), IEEE, 2011, pp. 92-97. [DOI:10.1109/ICEDSA.2011.5959046]
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