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In this paper, we present a 5T GC-eDRAM cell in FinFET technology. The memory structure is designed utilizing both p and n-type transistors to eliminate the clock feedthrough, multiple threshold voltages, and stack effect, thus lowering static power consumption. In the data path, a series of low power transistors are used to minimize the leakage current due to the stack effect. This allows achieving higher retention time and low static power consumption. The improved data retention time and reduced refresh frequency, refresh power, and retention power will be achieved, due to the slower failure of data 1 and 0. Our design has a new structure, high data retention time, as well as a low static and retention power among GC-eDRAMs with similar structures. The cell is, therefore, simultaneously classified as ultra-low-power and high-speed. Simulations of the proposed cell were performed at all dimensions less than 22 nm using the Hspice software. Compared to a 4T cell in 28 nm FD-SOI technology, the proposed cell in 20 nm FinFET has 195 times higher DRT, 80% lower static power consumption, and 48% smaller cell area.

Keywords: Embedded DRAM, Gain-cell, FinFET Technology, Data Retention Time, Retention Power

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